Hardware design of LIF with Latency neuron model with memristive STDP synapses

In this paper, the hardware implementation of a neuromorphic system is presented. This system is composed of a Leaky Integrate-and-Fire with Latency (LIFL) neuron and a Spike-Timing Dependent Plasticity (STDP) synapse. LIFL neuron model allows to encode more information than the common Integrate-and-Fire models, typically considered for neuromorphic implementations. In our system LIFL neuron is implemented using CMOS circuits while memristor is used for the implementation of the STDP synapse. A description of the entire circuit is provided. Finally, the capabilities of the proposed architecture have been evaluated by simulating a motif composed of three neurons and two synapses. The simulation results confirm the validity of the proposed system and its suitability for the design of more complex spiking neural network

Comparison of Low-Complexity Algorithms for Real-Time QRS Detection using Standard ECG Database

Today, thanks to the development of advanced wearable devices, it is possible to track patient conditions outside hospital setting for several days. One of the most important bio-signals used for health analysis is the electrocardiographic (ECG) signal. It provides information about the heart rate, rhythm, and morphology of heart. Many algorithms are proposed over years for automated ECG analysis. Due to their computational complexity, not all these techniques can be implemented on wearable devices for real-time ECG detection. In this frame, a particular interest is toward the algorithms for automatic QRS detection. Different algorithms have been presented in the literature. Among all, more suitable class for the implementation on embedded systems is based on the use of signal derivatives and thresholds. These algorithms are composed by pre-processing stage, for the noise removal, and decision stage for the QRS detection. In literature, the different algorithms were discriminated only with respect to their pre-processing stages. Furthermore, not all algorithms were tested with standard database: this makes the results difficult to compare and evaluate. Moreover, the algorithms performance in case of pathological behaviours was not compared. This paper is motivated by the need to perform a comparison of the whole algorithms, both pre-processing and decision stages, under a standard database (MIT-BIH ECG database of Physionet), either for non-pathological and pathological signals. The results confirm that the Pan & Tompkins algorithm has the best performance in terms of QRS complex detection. However, in some cases, its performance is comparable with the other algorithms ones. For this reason, in the applications in which the reduced of computational complexity is an important constraint, it is possible to implemented algorithms with comparable performance but with lesser complexity with respect to P&T algorithm

Energy Consumption Saving in Embedded Microprocessors Using Hardware Accelerators

This paper deals with the reduction of power consumption in embedded microprocessors. Computing power and energy efficiency are becoming the main challenges for embedded system applications. This is, in particular, the caseof wearable systems. When the power supply is provided by batteries, an important requirement for these systems is the long service life. This work investigates a method for the reduction of microprocessor energy consumption, based on the use of hardware accelerators. Their use allows to reduce the execution time and to decrease the clock frequency, so reducing the power consumption. In order to provide experimental results, authors analyze a case of study in the field of wearable devices for the processing of ECG signals. The experimental results show that the use of hardware accelerator significantly reduces the power consumption

Comparison between Trigonometric, and traditional DDS, in 90 nm technology

The Direct Digital frequency Synthesizer (DDS) is an architecture largely used for the generation of numeric sine and/or cosine waveforms in different applications. In this work, authors compare two different DDS architectures: the traditional architecture, based on the exploitation of quarter wave symmetry, and the Symon’s DDS (trigonometric DDS) presented in 2002. The two layout configurations have been implemented in 90 nm technology and compared in terms of area, speed and power consumption. Comparisons have been performed in terms of circuital complexity on architectures having the same Spurious Free Dynamic Range (SFDR) and phase resolution. Experiments show that the trigonometric architecture is very efficient in terms of area

comparison of low complexity algorithms for real time qrs detection using standard ecg database

Today, thanks to the development of advanced wearable devices, it is possible to track patient conditions outside hospital setting for several days. One of the most important bio-signals used for health analysis is the electrocardiographic (ECG) signal. It provides information about the heart rate, rhythm, and morphology of heart. Many algorithms are proposed over years for automated ECG analysis. Due to their computational complexity, not all these techniques can be implemented on wearable devices for real-time ECG detection. In this frame, a particular interest is toward the algorithms for automatic QRS detection. Different algorithms have been presented in the literature. Among all, more suitable class for the implementation on embedded systems is based on the use of signal derivatives and thresholds. These algorithms are composed by pre-processing stage, for the noise removal, and decision stage for the QRS detection. In literature, the different algorithms were discriminated only with respect to their pre-processing stages. Furthermore, not all algorithms were tested with standard database: this makes the results difficult to compare and evaluate. Moreover, the algorithms performance in case of pathological behaviours was not compared. This paper is motivated by the need to perform a comparison of the whole algorithms, both pre-processing and decision stages, under a standard database (MIT-BIH ECG database of Physionet), either for non-pathological and pathological signals. The results confirm that the Pan & Tompkins algorithm has the best performance in terms of QRS complex detection. However, in some cases, its performance is comparable with the other algorithms ones. For this reason, in the applications in which the reduced of computational complexity is an important constraint, it is possible to implemented algorithms with comparable performance but with lesser complexity with respect to P&T algorithm

Memristive and Memory Impedance Behavior in a Photo-Annealed ZnO–rGO Thin-Film Device

An oxygen-rich ZnO-reduced graphene oxide (rGO) thin film was synthesized using a photo-annealing technique from zinc precursor (ZnO)–graphene oxide (GO) sol–gel solution. X-ray diffraction (XRD) results show a clear characteristic peak corresponding to rGO. The scanning electron microscope (SEM) image of the prepared thin film shows an evenly distributed wrinkled surface structure. Transition Metal Oxide (TMO)-based memristive devices are nominees for beyond CMOS Non-Volatile Memory (NVRAM) devices. The two-terminal Metal–TMO (Insulator)–Metal (MIM) memristive device is fabricated using a synthesized ZnO–rGO as an active layer on fluorine-doped tin oxide (FTO)-coated glass substrate. Aluminum (Al) is deposited as a top metal contact on the ZnO–rGO active layer to complete the device. Photo annealing was used to reduce the GO to rGO to make the proposed method suitable for fabricating ZnO–rGO thin-film devices on flexible substrates. The electrical characterization of the Al–ZnO–rGO–FTO device confirms the coexistence of memristive and memimpedance characteristics. The coexistence of memory resistance and memory impedance in the same device could be valuable for developing novel programmable analog filters and self-resonating circuits and systems

A pseudo-softmax function for hardware-based high speed image classification

Abstract In this work a novel architecture, named pseudo-softmax, to compute an approximated form of the softmax function is presented. This architecture can be fruitfully used in the last layer of Neural Networks and Convolutional Neural Networks for classification tasks, and in Reinforcement Learning hardware accelerators to compute the Boltzmann action-selection policy. The proposed pseudo-softmax design, intended for efficient hardware implementation, exploits the typical integer quantization of hardware-based Neural Networks obtaining an accurate approximation of the result. In the paper, a detailed description of the architecture is given and an extensive analysis of the approximation error is performed by using both custom stimuli and real-world Convolutional Neural Networks inputs. The implementation results, based on CMOS standard-cell technology, compared to state-of-the-art architectures show reduced approximation errors